1. Technical Field
Embodiments of the present invention relate to a circuit for performing a design for testability (DFT) scan test, and more particularly, to an integrated circuit for performing a DFT scan test, which can perform different types of DFT scan tests, in a compression mode.
2. Discussion of Related Art
DFT is a name for design techniques that add certain testability features to a microelectronic hardware product design. The premise of the added features is that they make it easier to develop and apply manufacturing tests for the designed hardware. The purpose of manufacturing tests is to validate that the product hardware contains no defects that could, otherwise, adversely affect the product's correct functioning. Tests are applied at several steps in the hardware manufacturing flow and, for certain products, may also be used for hardware maintenance in the customer's environment. The tests may be driven by test programs that execute in Automatic Test Equipment (ATE) or inside the assembled system itself.
DFT circuits can be used to test integrated circuits (ICs). One method for delivering test data from chip inputs to internal circuits under test, and observing their outputs, is called a scan-design or a scan test. In a scan test, scan flip-flops in the design are connected in one or more scan chains to gain access to internal nodes of the chip. The scan test may be performed in a compression mode to reduce the testing time. However, when integrated circuits manufactured by different companies are interfaced together, it may not be possible to perform the scan test on the devices using the compression mode.